An integrated circuit (IC) is an assembly of discrete devices such as resistors, transistors, capacitors, etc. As an example, the transistor is a device comprising on-off properties that act as a power switch to the IC. A commonly known transistor to those skilled in the art is a metal-oxide-semiconductor field effect transistor (MOSFET).
Generally speaking, a typical MOSFET comprises a silicon substrate with a thin layer of thermally grown oxide used to isolate the substrate from conductive electrode. The metal electrode, generally referred to as a gate electrode, controls the on-off properties of the working device. The substrate including the gate electrode further comprises an oxidized gate dielectric layer on the sidewalls of the gate electrode and low-doped drain regions formed by implanting ions into the substrate of both sides of the gate dielectric layer. A spacer of an insulating layer is generally formed adjacent to opposite sidewalls of the gate electrode and the oxidized gate dielectric layer. An ion implantation process is performed to form a source and a drain at predetermined positions of the substrate besides the at least two spacers.
A conventional spacer commonly known to those skilled in the art is a D-shaped spacer. As the semiconductor industry continues to increase the density of devices manufacturable on a semiconductor substrate, the device features continue to shrink below the quarter-micron size. The critical dimensions between the gate electrodes are decreased, making it more difficult to achieve void-free fill between the spacers adjacent to the gate electrodes. In addition, channel stress-related and silicide stress-related problems increase with decreasing dimension. It is desired to fabricate semiconductor devices using reliable processing methods including a reduction in the number of steps required to fabricate a semiconductor device, reduced defects, lower thermal budget, reduced channel stress, and reduced resistivity at the source/drain region.
The disclosed invention provides space methods of forming this spacer, and more specifically a method of forming a spacer.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the Figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or analogous elements.